//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : over sample the input data with 8-phases 311M clock
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths

module FRM_RSCRM4(
   input                         FRM_RESET,
   input                         FRM_RXCLK,

   input[1:0]                    RSCRM4_IN_FMCNT4,
   input[8:0]                    RSCRM4_IN_FMCNT270,
   input[3:0]                    RSCRM4_IN_FMCNT9,
   input[7:0]                    RSCRM4_IN_DATA,
   input                         RSCRM4_IN_DEN,
   input                         RSCRM4_IN_OOF,

   output reg[7:0]               RSCRM4_OUT_DATA,
   output reg                    RSCRM4_OUT_DEN,
   output reg[1:0]               RSCRM4_OUT_FMCNT4,
   output reg[8:0]               RSCRM4_OUT_FMCNT270,
   output reg[3:0]               RSCRM4_OUT_FMCNT9,
   output reg[3:0]               RSCRM4_OUT_B1ERR,
   output reg                    RSCRM4_OUT_B1ERR_EN
   );


reg[7:0]                         SCRM_VECTOR;
reg                              SCRM_EN;


reg[7:0]                         B1_CALCULATING;
reg[7:0]                         B1_RESULT;
reg[7:0]                         B1_ERR_VECTOR;

always @( RSCRM4_IN_FMCNT270 or RSCRM4_IN_FMCNT9) begin
   if ( RSCRM4_IN_FMCNT270[8:0] <9'd9 && RSCRM4_IN_FMCNT9[3:0]==4'd0 )
      SCRM_EN                                       <= 1'b0;
   else
      SCRM_EN                                       <= 1'b1;
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      SCRM_VECTOR[7:0]                              <= 8'd0;
   else begin
      if ( RSCRM4_IN_FMCNT4[1:0]==2'd3 && RSCRM4_IN_FMCNT270[8:0]==9'd269 && RSCRM4_IN_FMCNT9[3:0]==4'd8 && RSCRM4_IN_DEN==1'b1)
         SCRM_VECTOR[7:0]                           <= 8'hfe;
      else if ( SCRM_EN==1'b1 && RSCRM4_IN_DEN==1'b1 ) begin
         SCRM_VECTOR[7]                             <= SCRM_VECTOR[6] ^ SCRM_VECTOR[5];
         SCRM_VECTOR[6]                             <= SCRM_VECTOR[5] ^ SCRM_VECTOR[4];
         SCRM_VECTOR[5]                             <= SCRM_VECTOR[4] ^ SCRM_VECTOR[3];
         SCRM_VECTOR[4]                             <= SCRM_VECTOR[3] ^ SCRM_VECTOR[2];
         SCRM_VECTOR[3]                             <= SCRM_VECTOR[2] ^ SCRM_VECTOR[1];
         SCRM_VECTOR[2]                             <= SCRM_VECTOR[1] ^ SCRM_VECTOR[0];
         SCRM_VECTOR[1]                             <= SCRM_VECTOR[0] ^ (SCRM_VECTOR[6] ^ SCRM_VECTOR[5]);
         SCRM_VECTOR[0]                             <= (SCRM_VECTOR[6] ^ SCRM_VECTOR[5]) ^ (SCRM_VECTOR[5] ^ SCRM_VECTOR[4]);
      end
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 ) begin
      RSCRM4_OUT_DEN                                <= 1'b0;
      RSCRM4_OUT_FMCNT4[1:0]                        <= 2'd0;
      RSCRM4_OUT_FMCNT270[8:0]                      <= 9'd0;
      RSCRM4_OUT_FMCNT9[3:0]                        <= 4'd0;
      RSCRM4_OUT_DATA[7:0]                          <= 4'd0;
   end
   else begin
      RSCRM4_OUT_DEN                                <= RSCRM4_IN_DEN;
      RSCRM4_OUT_FMCNT4[1:0]                        <= RSCRM4_IN_FMCNT4[1:0];
      RSCRM4_OUT_FMCNT270[8:0]                      <= RSCRM4_IN_FMCNT270[8:0];
      RSCRM4_OUT_FMCNT9[3:0]                        <= RSCRM4_IN_FMCNT9[3:0];
      if ( RSCRM4_IN_OOF==1'b1 )
         RSCRM4_OUT_DATA[7:0]                       <= 8'hff;
      else if ( SCRM_EN==1'b0 )
         RSCRM4_OUT_DATA[7:0]                       <= RSCRM4_IN_DATA[7:0];
      else
         RSCRM4_OUT_DATA[7:0]                       <= RSCRM4_IN_DATA[7:0] ^ SCRM_VECTOR[7:0];
   end
end




always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      B1_CALCULATING[7:0]                           <= 8'd0;
   else begin
      if ( RSCRM4_IN_FMCNT4[1:0]==2'd3 && RSCRM4_IN_FMCNT270[8:0]==9'd269 && RSCRM4_IN_FMCNT9[3:0]==4'd8 && RSCRM4_IN_DEN==1'b1 )
         B1_CALCULATING[7:0]                        <= 8'd0;
      else if ( RSCRM4_IN_DEN==1'b1 )
         B1_CALCULATING[7:0]                        <= B1_CALCULATING[7:0] ^ RSCRM4_IN_DATA[7:0];
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      B1_RESULT[7:0]                                <= 8'd0;
   else begin
      if ( RSCRM4_IN_FMCNT4[1:0]==2'd3 && RSCRM4_IN_FMCNT270[8:0]==9'd269 && RSCRM4_IN_FMCNT9[3:0]==4'd8 && RSCRM4_IN_DEN==1'b1 )
         B1_RESULT[7:0]                             <= B1_CALCULATING[7:0] ^ RSCRM4_IN_DATA[7:0];
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      B1_ERR_VECTOR[7:0]                            <= 8'd0;
   else begin
      if ( RSCRM4_OUT_FMCNT4[1:0]==2'd0 && RSCRM4_OUT_FMCNT270[8:0]==9'd0 && RSCRM4_OUT_FMCNT9[3:0]==4'd1 && RSCRM4_OUT_DEN==1'b1 )
         B1_ERR_VECTOR[7:0]                         <= B1_RESULT[7:0] ^ RSCRM4_OUT_DATA[7:0];
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      RSCRM4_OUT_B1ERR[3:0]                          <= 4'd0;
   else
      RSCRM4_OUT_B1ERR[3:0]                          <= {3'd0, B1_ERR_VECTOR[0]} + {3'd0, B1_ERR_VECTOR[1]} + {3'd0, B1_ERR_VECTOR[2]} + {3'd0, B1_ERR_VECTOR[3]} + {3'd0, B1_ERR_VECTOR[4]} + {3'd0, B1_ERR_VECTOR[5]} + {3'd0, B1_ERR_VECTOR[6]} +{3'd0, B1_ERR_VECTOR[7]};
end
always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      RSCRM4_OUT_B1ERR_EN                            <= 1'b0;
   else
      RSCRM4_OUT_B1ERR_EN                            <= RSCRM4_IN_FMCNT9[3:0]==4'd2;
end

/*
//  +++++++++++++++++++++++++++++++++++ Section 0 : Detect the frame symbol "F6F62828"  +++++++++++++++++++++++++++++++++++++++  //
wire[15:0]                      match_input_data;
wire                            match_input_search_restart;
reg[15:0]                       match_output_data;
reg                             match_output_hit;

reg[3:0]                        match_delmt_bit_selc;
reg[47:0]                       match_shift_regs;
reg[15:0]                       match_hit_vector;
reg[3:0]                        match_hit_code;

  assign  match_input_data[15:0]      = HSI_RX_DATA[15:0];
  assign  match_input_search_restart  = fsck_output_search_restart;

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      match_shift_regs[47:0]                  <= 48'd0;
   else
      match_shift_regs[47:0]                  <= {match_shift_regs[31:0], match_input_data[15:0]};
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      match_hit_vector[15:0]                  <= 16'd0;
   else begin
      match_hit_vector[15]                    <= (match_shift_regs[47:16]==32'hf6f6_2828);
      match_hit_vector[14]                    <= (match_shift_regs[46:15]==32'hf6f6_2828);
      match_hit_vector[13]                    <= (match_shift_regs[45:14]==32'hf6f6_2828);
      match_hit_vector[12]                    <= (match_shift_regs[44:13]==32'hf6f6_2828);
      match_hit_vector[11]                    <= (match_shift_regs[43:12]==32'hf6f6_2828);
      match_hit_vector[10]                    <= (match_shift_regs[42:11]==32'hf6f6_2828);
      match_hit_vector[9]                     <= (match_shift_regs[41:10]==32'hf6f6_2828);
      match_hit_vector[8]                     <= (match_shift_regs[40:9] ==32'hf6f6_2828);
      match_hit_vector[7]                     <= (match_shift_regs[39:8] ==32'hf6f6_2828);
      match_hit_vector[6]                     <= (match_shift_regs[38:7] ==32'hf6f6_2828);
      match_hit_vector[5]                     <= (match_shift_regs[37:6] ==32'hf6f6_2828);
      match_hit_vector[4]                     <= (match_shift_regs[36:5] ==32'hf6f6_2828);
      match_hit_vector[3]                     <= (match_shift_regs[35:4] ==32'hf6f6_2828);
      match_hit_vector[2]                     <= (match_shift_regs[34:3] ==32'hf6f6_2828);
      match_hit_vector[1]                     <= (match_shift_regs[33:2] ==32'hf6f6_2828);
      match_hit_vector[0]                     <= (match_shift_regs[32:1] ==32'hf6f6_2828);
   end
end

always @( match_hit_vector ) begin
   case ( match_hit_vector[15:0] )
   16'h8000: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_1111;
   16'h4000: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_1110;
   16'h2000: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_1101;
   16'h1000: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_1100;
   16'h0800: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_1011;
   16'h0400: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_1010;
   16'h0200: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_1001;
   16'h0100: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_1000;
   16'h0080: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_0111;
   16'h0040: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_0110;
   16'h0020: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_0101;
   16'h0010: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_0100;
   16'h0008: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_0011;
   16'h0004: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_0010;
   16'h0002: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_0001;
   16'h0001: { match_output_hit, match_hit_code[3:0]}       <= 5'b1_0000;
   default:  { match_output_hit, match_hit_code[3:0]}       <= 5'd0;
   endcase
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      match_delmt_bit_selc[3:0]                      <= 4'd0;
   else begin
      if ( match_input_search_restart==1'b1 && match_output_hit==1'b1 )
         match_delmt_bit_selc[3:0]                   <= match_hit_code[3:0];
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      match_output_data[15:0]                        <= 16'd0;
   else begin
      case (match_delmt_bit_selc[3:0])
      4'hF: match_output_data[15:0]                  <= match_shift_regs[31:16];
      4'hE: match_output_data[15:0]                  <= match_shift_regs[30:15];
      4'hD: match_output_data[15:0]                  <= match_shift_regs[29:14];
      4'hC: match_output_data[15:0]                  <= match_shift_regs[28:13];
      4'hB: match_output_data[15:0]                  <= match_shift_regs[27:12];
      4'hA: match_output_data[15:0]                  <= match_shift_regs[26:11];
      4'h9: match_output_data[15:0]                  <= match_shift_regs[25:10];
      4'h8: match_output_data[15:0]                  <= match_shift_regs[24:9];
      4'h7: match_output_data[15:0]                  <= match_shift_regs[23:8];
      4'h6: match_output_data[15:0]                  <= match_shift_regs[22:7];
      4'h5: match_output_data[15:0]                  <= match_shift_regs[21:6];
      4'h4: match_output_data[15:0]                  <= match_shift_regs[20:5];
      4'h3: match_output_data[15:0]                  <= match_shift_regs[19:4];
      4'h2: match_output_data[15:0]                  <= match_shift_regs[18:3];
      4'h1: match_output_data[15:0]                  <= match_shift_regs[17:2];
      4'h0: match_output_data[15:0]                  <= match_shift_regs[16:1];
      default: ;
      endcase
   end
end


//  +++++++++++++++++++++++++++++++++++ Section 1 : frame symbol check and OOF/LOF detect  +++++++++++++++++++++++++++++++++++++++  //
wire[15:0]                      fsck_input_data;
wire                            fsck_input_hit;
wire                            fsck_output_search_restart;
wire[15:0]                      fsck_output_data;
reg[2:0]                        fsck_output_framer_count8;
reg[8:0]                        fsck_output_framer_count270;
reg[3:0]                        fsck_output_framer_count9;

reg[2:0]                        fsck_fsm;
reg[1:0]                        fsck_mismatch_cnt3;
reg                             fsck_mismatch_f6, fsck_mismatch_28;

  assign fsck_input_data[15:0]      = match_output_data[15:0];
  assign fsck_output_data[15:0]     = fsck_input_data;
  assign fsck_input_hit             = match_output_hit;
  assign MPI_FRM_OOF                = fsck_output_search_restart;

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      fsck_fsm[2:0]                            <= 3'd0;
   else begin
      case (fsck_fsm[2:0])
      3'd0: begin                // OOF state
         if ( fsck_input_hit==1'b1 )
            fsck_fsm[2:0]                      <= 3'd1;
      end
      3'd1: begin                // the first frame, no operation
         if ( fsck_output_framer_count8[2:0]==3'b111 && fsck_output_framer_count270[8:0]==9'd269 && fsck_output_framer_count9[3:0]==4'd8 )
            fsck_fsm[2:0]                      <= 3'd3;
      end
      3'd3: begin
         if ( fsck_mismatch_cnt3[1:0]==2'd3 )
            fsck_fsm[2:0]                      <= 3'd4;
      end
      3'd4: fsck_fsm[2:0]                      <= 3'd0;      // restart frame symbol detect
      default: fsck_fsm[2:0]                   <= 3'd0;
      endcase
   end
end
  assign fsck_output_search_restart = (fsck_fsm[2:0]==3'd0);


always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      fsck_output_framer_count8[2:0]                  <= 3'd0;
   else begin
      if ( fsck_input_hit==1'b1 && fsck_fsm[2:0]==3'd0 )
         fsck_output_framer_count8[2:0]               <= 3'd1;
      else
         fsck_output_framer_count8[2:0]               <= fsck_output_framer_count8[2:0] +3'd1;
   end
end
always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      fsck_output_framer_count270[8:0]                <= 9'd0;
   else begin
      if ( fsck_input_hit==1'b1 && fsck_fsm[2:0]==3'd0 )
         fsck_output_framer_count270[8:0]             <= 9'd3;
      else if ( fsck_output_framer_count8[2:0]==3'b111 ) begin
         if ( fsck_output_framer_count270[8:0]==9'd269 )
            fsck_output_framer_count270[8:0]          <= 9'd0;
         else
            fsck_output_framer_count270[8:0]          <= fsck_output_framer_count270[8:0] +9'd1;
      end
   end
end
always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      fsck_output_framer_count9[3:0]                  <= 4'd0;
   else begin
      if ( fsck_input_hit==1'b1 && fsck_fsm[2:0]==3'd0 )
         fsck_output_framer_count9[3:0]               <= 4'd0;
      else if ( fsck_output_framer_count8[2:0]==3'b111 && fsck_output_framer_count270[8:0]==9'd269 ) begin
         if ( fsck_output_framer_count9[3:0]==4'd8 )
            fsck_output_framer_count9[3:0]            <= 4'd0;
         else
            fsck_output_framer_count9[3:0]            <= fsck_output_framer_count9[3:0] +4'd1;
      end
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      fsck_mismatch_f6                         <= 1'b0;
   else begin
      if ( fsck_output_framer_count8[2:0]==3'b111 && fsck_output_framer_count270[8:0]==9'd269 && fsck_output_framer_count9[3:0]==4'd8 )
         fsck_mismatch_f6                      <= 1'b0;
      else if ( fsck_output_framer_count270[8:0]==9'd0 && fsck_input_data[15:0]!=16'hf6f6 && fsck_output_framer_count9[3:0]==4'd0)
         fsck_mismatch_f6                      <= 1'd1;
      else if ( fsck_output_framer_count270[8:0]==9'd1 && fsck_input_data[15:0]!=16'hf6f6 && fsck_output_framer_count9[3:0]==4'd0)
         fsck_mismatch_f6                      <= 1'd1;
      else if ( fsck_output_framer_count270[8:0]==9'd2 && fsck_input_data[15:0]!=16'hf6f6 && fsck_output_framer_count9[3:0]==4'd0)
         fsck_mismatch_f6                      <= 1'd1;
   end
end
always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      fsck_mismatch_28                         <= 1'b0;
   else begin
      if ( fsck_output_framer_count8[2:0]==3'b111 && fsck_output_framer_count270[8:0]==9'd269 && fsck_output_framer_count9[3:0]==4'd8 )
         fsck_mismatch_28                      <= 1'b0;
      else if ( fsck_output_framer_count270[8:0]==9'd3 && fsck_input_data[15:0]!=16'h2828 && fsck_output_framer_count9[3:0]==4'd0)
         fsck_mismatch_28                      <= 1'd1;
      else if ( fsck_output_framer_count270[8:0]==9'd4 && fsck_input_data[15:0]!=16'h2828 && fsck_output_framer_count9[3:0]==4'd0)
         fsck_mismatch_28                      <= 1'd1;
      else if ( fsck_output_framer_count270[8:0]==9'd5 && fsck_input_data[15:0]!=16'h2828 && fsck_output_framer_count9[3:0]==4'd0)
         fsck_mismatch_28                      <= 1'd1;
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      fsck_mismatch_cnt3[1:0]                        <= 2'd0;
   else begin
      if ( fsck_fsm[2:0]==3'd3 ) begin
         if ( fsck_output_framer_count8[2:0]==3'b111 && fsck_output_framer_count270[8:0]==9'd8 && fsck_output_framer_count9[3:0]==4'd0 ) begin
            if ( fsck_mismatch_f6==1'b1 || fsck_mismatch_28==1'b1 )
               fsck_mismatch_cnt3[1:0]               <= fsck_mismatch_cnt3[1:0] +2'd1;
            else
               fsck_mismatch_cnt3[1:0]               <= 2'd0;
         end
      end
      else begin
               fsck_mismatch_cnt3[1:0]               <= 2'd0;
      end
   end
end






//  +++++++++++++++++++++++++++++++++++ Section 0 : B1 Calc  +++++++++++++++++++++++++++++++++++++++  //
wire[2:0]                       b1scrm_input_framer_count8;
wire[8:0]                       b1scrm_input_framer_count270;
wire[3:0]                       b1scrm_input_framer_count9;
wire[15:0]                      b1scrm_input_data;

reg[7:0]                        b1scrm_b1result;
reg[7:0]                        b1scrm_b1calculating;
reg[15:0]                       b1scrm_scram_vector;
reg[7:0]                        b1scrm_b1err_vector;

reg[15:0]                       b1scrm_output_data;
reg[2:0]                        b1scrm_output_framer_cnt8;
reg[8:0]                        b1scrm_output_framer_cnt270;
reg[3:0]                        b1scrm_output_framer_cnt9;
reg[3:0]                        b1scrm_output_b1err;
reg                             b1scrm_output_b1err_en;


  assign b1scrm_input_framer_count8[2:0]     = fsck_output_framer_count8[2:0];
  assign b1scrm_input_framer_count270[8:0]   = fsck_output_framer_count270[8:0];
  assign b1scrm_input_framer_count9[3:0]     = fsck_output_framer_count9[3:0];
  assign b1scrm_input_data[15:0]             = fsck_output_data[15:0];
 
  assign FRM_RX_FRAMER_CNT8[2:0]    = b1scrm_output_framer_cnt8[2:0];
  assign FRM_RX_FRAMER_CNT270[8:0]  = b1scrm_output_framer_cnt270[8:0];
  assign FRM_RX_FRAMER_CNT9[3:0]    = b1scrm_output_framer_cnt9[3:0];
  assign FRM_RX_DATA[15:0]          = b1scrm_output_data[15:0];
  assign MPI_FRM_B1ERR_EN           = b1scrm_output_b1err_en;
  assign MPI_FRM_B1ERR[3:0]         = b1scrm_output_b1err[3:0];

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      b1scrm_b1calculating[7:0]                  <= 8'd0;
   else begin
      if ( b1scrm_input_framer_count9[3:0]==4'd8 && b1scrm_input_framer_count270[8:0]==9'd269 && b1scrm_input_framer_count8[2:0]==3'd7)
         b1scrm_b1calculating[7:0]               <= 8'd0;
      else begin
         b1scrm_b1calculating[7]                 <= (b1scrm_input_data[7] ^ b1scrm_input_data[15]) ^ b1scrm_b1calculating[7];
         b1scrm_b1calculating[6]                 <= (b1scrm_input_data[6] ^ b1scrm_input_data[14]) ^ b1scrm_b1calculating[6];
         b1scrm_b1calculating[5]                 <= (b1scrm_input_data[5] ^ b1scrm_input_data[13]) ^ b1scrm_b1calculating[5];
         b1scrm_b1calculating[4]                 <= (b1scrm_input_data[4] ^ b1scrm_input_data[12]) ^ b1scrm_b1calculating[4];
         b1scrm_b1calculating[3]                 <= (b1scrm_input_data[3] ^ b1scrm_input_data[11]) ^ b1scrm_b1calculating[3];
         b1scrm_b1calculating[2]                 <= (b1scrm_input_data[2] ^ b1scrm_input_data[10]) ^ b1scrm_b1calculating[2];
         b1scrm_b1calculating[1]                 <= (b1scrm_input_data[1] ^ b1scrm_input_data[9])  ^ b1scrm_b1calculating[1];
         b1scrm_b1calculating[0]                 <= (b1scrm_input_data[0] ^ b1scrm_input_data[8])  ^ b1scrm_b1calculating[0];
      end
   end
end
always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      b1scrm_b1result[7:0]                          <= 8'd0;
   else begin
      if ( b1scrm_input_framer_count9[3:0]==4'd8 && b1scrm_input_framer_count270[8:0]==9'd269 && b1scrm_input_framer_count8[2:0]==3'd7) begin
         b1scrm_b1result[7]                      <= (b1scrm_input_data[7] ^ b1scrm_input_data[15]) ^ b1scrm_b1calculating[7];
         b1scrm_b1result[6]                      <= (b1scrm_input_data[6] ^ b1scrm_input_data[14]) ^ b1scrm_b1calculating[6];
         b1scrm_b1result[5]                      <= (b1scrm_input_data[5] ^ b1scrm_input_data[13]) ^ b1scrm_b1calculating[5];
         b1scrm_b1result[4]                      <= (b1scrm_input_data[4] ^ b1scrm_input_data[12]) ^ b1scrm_b1calculating[4];
         b1scrm_b1result[3]                      <= (b1scrm_input_data[3] ^ b1scrm_input_data[11]) ^ b1scrm_b1calculating[3];
         b1scrm_b1result[2]                      <= (b1scrm_input_data[2] ^ b1scrm_input_data[10]) ^ b1scrm_b1calculating[2];
         b1scrm_b1result[1]                      <= (b1scrm_input_data[1] ^ b1scrm_input_data[9])  ^ b1scrm_b1calculating[1];
         b1scrm_b1result[0]                      <= (b1scrm_input_data[0] ^ b1scrm_input_data[8])  ^ b1scrm_b1calculating[0];
      end
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      b1scrm_scram_vector[15:0]                 <= 16'd0;
   else begin
      if ( b1scrm_input_framer_count9[3:0]==4'd0 &&  b1scrm_input_framer_count270[8:0]<9'd9)
         b1scrm_scram_vector[15:0]              <= 16'hfe04;
      else begin
         b1scrm_scram_vector[15]                <= b1scrm_scram_vector[6] ^ b1scrm_scram_vector[5];
         b1scrm_scram_vector[14]                <= b1scrm_scram_vector[5] ^ b1scrm_scram_vector[4];
         b1scrm_scram_vector[13]                <= b1scrm_scram_vector[4] ^ b1scrm_scram_vector[3];
         b1scrm_scram_vector[12]                <= b1scrm_scram_vector[3] ^ b1scrm_scram_vector[2];
         b1scrm_scram_vector[11]                <= b1scrm_scram_vector[2] ^ b1scrm_scram_vector[1];
         b1scrm_scram_vector[10]                <= b1scrm_scram_vector[1] ^ b1scrm_scram_vector[0];
         b1scrm_scram_vector[9]                 <= b1scrm_scram_vector[0] ^ b1scrm_scram_vector[6] ^ b1scrm_scram_vector[5];
         b1scrm_scram_vector[8]                 <= b1scrm_scram_vector[6] ^ b1scrm_scram_vector[4];
         b1scrm_scram_vector[7]                 <= b1scrm_scram_vector[5] ^ b1scrm_scram_vector[3];
         b1scrm_scram_vector[6]                 <= b1scrm_scram_vector[4] ^ b1scrm_scram_vector[2];
         b1scrm_scram_vector[5]                 <= b1scrm_scram_vector[3] ^ b1scrm_scram_vector[1];
         b1scrm_scram_vector[4]                 <= b1scrm_scram_vector[2] ^ b1scrm_scram_vector[0];
         b1scrm_scram_vector[3]                 <= b1scrm_scram_vector[1] ^ b1scrm_scram_vector[6] ^ b1scrm_scram_vector[5];
         b1scrm_scram_vector[2]                 <= b1scrm_scram_vector[0] ^ b1scrm_scram_vector[5] ^ b1scrm_scram_vector[4];
         b1scrm_scram_vector[1]                 <= b1scrm_scram_vector[6] ^ b1scrm_scram_vector[5] ^ b1scrm_scram_vector[4] ^ b1scrm_scram_vector[3];
         b1scrm_scram_vector[0]                 <= b1scrm_scram_vector[5] ^ b1scrm_scram_vector[4] ^ b1scrm_scram_vector[3] ^ b1scrm_scram_vector[2];
      end
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 ) begin
      b1scrm_output_data[15:0]                  <= 16'd0;
      b1scrm_output_framer_cnt8[2:0]            <= 3'd0;
      b1scrm_output_framer_cnt270[8:0]          <= 8'd0;
      b1scrm_output_framer_cnt9[3:0]            <= 4'd0;
   end
   else begin
      b1scrm_output_framer_cnt8[2:0]            <= b1scrm_input_framer_count8[2:0];
      b1scrm_output_framer_cnt270[8:0]          <= b1scrm_input_framer_count270[8:0];
      b1scrm_output_framer_cnt9[3:0]            <= b1scrm_input_framer_count9[3:0];
      if ( b1scrm_input_framer_count9[3:0]==4'd0 &&  b1scrm_input_framer_count270[8:0]<9'd9 )
         b1scrm_output_data[15:0]               <= b1scrm_input_data[15:0];
      else
         b1scrm_output_data[15:0]               <= b1scrm_input_data[15:0] ^ b1scrm_scram_vector[15:0];
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 ) begin
      b1scrm_b1err_vector[7:0]                   <= 8'd0;
      b1scrm_output_b1err_en                     <= 1'b0;
      b1scrm_output_b1err[3:0]                   <= 4'd0;
   end
   else begin
      b1scrm_output_b1err_en                     <= ( b1scrm_input_framer_count9[3:0]==4'd2);
      b1scrm_output_b1err[3:0]                   <= {3'd0, b1scrm_b1err_vector[0]} +{3'd0, b1scrm_b1err_vector[1]} +{3'd0, b1scrm_b1err_vector[2]} +{3'd0, b1scrm_b1err_vector[3]} +{3'd0, b1scrm_b1err_vector[4]} +{3'd0, b1scrm_b1err_vector[5]} +{3'd0, b1scrm_b1err_vector[6]} +{3'd0, b1scrm_b1err_vector[7]};
      if ( b1scrm_output_framer_cnt9[3:0]==4'd1 && b1scrm_output_framer_cnt270[8:0]==9'd0 && b1scrm_output_framer_cnt8[2:0]==3'd0 )
         b1scrm_b1err_vector[7:0]                <= b1scrm_b1result[7:0] ^ b1scrm_output_data[15:8];
   end
end
*/
endmodule


